This pin is the chip select input connecting to the MCU. Select appropriate logic setting as described in the following table. It should match with the MCU interface voltage level and must be connected to external source. Low voltage power supply and power supply for interface logic level in both Low Voltage I/O and 5V I/O application. In 5V IO application (internal VDD is enabled), VDD is regulated internally from VDDIO.Ī capacitor should be connected between VDD and VSS under all circumstances. In LV IO application (internal VDD is disabled), this is a power input pin. VDD can be supplied externally or regulated internally. This pin is used to change the mapping between the display data column address and the Segment driver. This pin is used to determine the Common output scanning direction. When this pin is pulled LOW, internal VDD regulator is disabled (Low voltage I/O application). When this pin is pulled HIGH, internal VDD regulator is enabled (5V I/O application). Internal VDD regulator selection pin in 5V I/O application mode. When external VSL is used, connect with resistor and diode to ground (details depend on application). When external VSL is not used, this pin should be left open. This is segment voltage (output low level) reference pin.
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